1. Field of the Invention
This invention relates to integrated circuit output signals and, more particularly, to output signal drive strength compensation.
2. Description of the Related Art
Integrated circuit parameters may vary with factors such as temperature, voltage and frequency. One circuit parameter of interest is the drive strength of an output driver stage. The output drive strength of a signal is typically matched to the circuit that is being driven. For example, a signal trace that is on a circuit board may have an intrinsic impedance associated with it. In some cases, a board designer may place a resistor that matches the impedance of the trace in series with the output driver and the device receiving the signal. This may provide a way to minimize any excess drive current in the circuit. Thus, integrated circuit designers may try to match the output impedance by designing resistive circuits in the circuit pad with the correct impedance.
In a static environment, this design practice may work. However, as mentioned above, circuit parameters such as resistors on an integrated circuit, may vary with temperature. Thus if the resistive circuits in the output pad change, signal degradation may result. This degradation may be more pronounced at higher frequencies. Therefore, it may be necessary to provide a mechanism to compensate the drive strength of the output driver circuits in an integrated circuit.
There may be many ways to compensate the drive strength of an output driver. Some compensation mechanisms inhibit or stop the output signal while the drive strength is modified. This may work unless it is undesirable to stop the signal to wait for the drive strength to change. Other compensation mechanisms may change the drive strength while the signal is being output. Depending on the signal, this may cause undesirable glitches in the output signal. Thus another method of compensating the drive strength of an output driver may be desirable.
Various embodiments of a circuit for dynamic signal drive strength compensation are disclosed. In one embodiment, a circuit for compensating the drive strength of an output signal includes an output driver stage including a driver circuit and a drive strength control circuit. The driver circuit may be selectively enabled depending upon a drive strength indicator signal. The driver circuit includes a P-channel transistor which has a P input which is controlled by a P-channel control signal. The driver circuit also includes an N-channel transistor which has an N input which is controlled by an N-channel control signal. The drive strength control circuit may generate the respective P-channel and N-channel control signals. The P-channel control signal is dependent upon an input signal and a P-channel enable signal and the N-channel control signal is dependent upon the input signal and an N-channel enable signal. The P-channel enable signal is dependent upon the drive strength indicator signal and the P-channel control signal is prevented from changing while the P-channel transistor is turned on. The N-channel enable signal is dependent upon the drive strength indicator signal and the N-channel control signal is prevented from changing while the N-channel transistor is turned on.
In one particular implementation, the output driver stage further includes a plurality of additional driver circuits. Each of the plurality of additional driver circuits is coupled in parallel to the driver circuit and includes a P-channel transistor and an N-channel transistor. Each of the plurality of additional driver circuits may also be selectively enabled depending upon the drive strength indicator signal. The plurality of additional P-channel transistors is controlled by a plurality of additional P-channel control signals and the plurality of additional N-channel transistors is controlled by a plurality of additional N-channel control signals.
The drive strength control circuit may further generate the plurality of additional P-channel and N-channel control signals. The plurality of additional P-channel control signals are prevented from changing while the plurality of additional P-channel transistors are turned on and the plurality of additional N-channel control signals are prevented from changing while the plurality of additional N-channel transistors are turned on.